The present invention relates to a semiconductor device and its manufacturing method, especially to a semiconductor device having a circuit to relieve a defect using copper interconnection and a method for manufacturing the device.
In semiconductor devices, copper (Cu) interconnection is widely adopted in order to reduce signal delay in interconnections by lowering resistance in interconnections and to increase electromigration resistance. Especially copper interconnections are becoming a mainstream in high performance logic large-scale integration (LSI).
On the other hand, in LSIs having memories in a mixed manner, the adoption of redundant construction having a built-in defect relieving circuit in order to increase process yield is common technology. In the redundancy construction, a spare cell is used by replacing a defective cell found.
The metal fuse usually employs a metal interconnection layer which is one layer below the top metal interconnection layer. This is because the top layer is not well protected and not reliable because the metal is degraded by contact with the atmosphere, etc., and the top layer is not suited to be blown since the film thickness of the metal interconnection layer on the top layer is large because it is often used as a power line.
Accordingly, in order to blow a metal fuse, it is necessary to remove the first protective insulating film such as the interlayer insulating film and passivation film which exist above the metal fuse which are an obstacle for blowing a fuse. This process of removing an interlayer film and the first protective insulating film on a metal fuse is called the “fuse window opening process”.
The conventional window opening process will be explained below.
FIGS. 14 and 15 are cross sectional views of the device showing the conventional window opening process.
FIG. 14 is a sectional view of a conventional semiconductor device with a four-layer interconnection structure. This four-layer interconnection structure includes the first and second interlayer insulating film 16 and 19, the first interconnection layer 21, a silicon nitride film as an antioxidant film (Si3N4 film) 22, the third interlayer insulating film 23, the second interconnection layer 27, a silicon nitride film (Si3N4 film) 28, the fourth interlayer insulating film 29, the third interconnection layer 32, a silicon nitride film (Si3N4 film) 33, the fifth interlayer insulating film 34, the fourth interconnection layer 37, silicon nitride film (Si3N4 film) 38, etc. which are built up on the semiconductor substrate 11 where devices are formed. A bonding pad section 41 and a passivation film 39 are formed on the top layer.
Such semiconductor devices are manufactured by the following process.
At first, in order to form a fuse window opening, photoresist 100 is applied to the entire part then patterning is performed by photolithography so that the area except a fuse window opening is covered with the photoresist 100. A passivation film 39, a thin silicon nitride film 38 and the fifth interlayer insulating film 34 are etched in a method such as RIE (Reactive Ton Etching) using the resist 100 as an etching mask in order to open a fuse window 110. In this state, the positions of a side wall 101 of the resist 100 at the opening 110, a side wall 102 of the passivation film 39, a side wall 103 of the thin silicon nitride film 38 and a side wall 104 of the fifth interlayer insulating film 34 are continuous.
Finally, the resist 100 is removed and a polyimide film 120 as a surface protective film is formed on the passivation film 39 except a bonding pad section 41 and the fuse window 110. At this time, the positions of a side wall 121 of a polyimide film 120 and a side wall 102 of the passivation film 39 are not matched. This creates a probelam that the fuse window a opening becomes narrower as explained later.